 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| RTL8208 REALTEK SINGLE CHIP OCTAL 10/100 MBPS FAST ETHERNET TRANSCEIVER RTL8208 1. Features........................................................................ 2 2. General Description .................................................... 2 3. Block Diagram............................................................. 3 4. Pin Assignments........................................................... 4 5. Pin Description ............................................................ 6 5.1 Media Connection Pins .......................................... 6 5.2 Power and Ground Pins.......................................... 6 5.3 Miscellaneous Pins................................................. 7 5.4 RMII/SMII/SS-SMII Pins ...................................... 8 5.5 SMI (Serial Management Interface) Pins ............... 9 5.6 LED Pins ................................................................ 9 5.7 Mode Control Pins ............................................... 10 5.8 Reserved Pins ....................................................... 11 6. Register Descriptions ................................................ 12 6.1 Register0: Control ................................................ 12 6.2 Register1: Status................................................... 14 6.3 Register2: PHY Identifier 1 Register.................... 15 6.4 Register3: PHY Identifier 2 Register.................... 15 6.5 Register4: Auto-Negotiation Advertisement ........ 16 6.6 Register5: Auto-Negotiation Link Partner Ability......... 17 6.7 Register6: Auto-Negotiation Expansion............... 18 7. Functional Description ............................................. 19 7.1 General ................................................................. 19 7.1.1 SMI (Serial Management Interface) ............. 19 7.1.2 Port Pair Loop Back Mode (PP-LPBK)........ 19 7.1.3 PHY Address ................................................ 20 7.1.4 Auto-Negotiation .......................................... 20 7.1.5 Full-Duplex Flow Control ............................ 20 7.2 Initialization and Setup......................................... 20 7.2.1 Reset ............................................................. 20 7.2.2 Setup and configuration................................ 20 7.3 10Base-T .............................................................. 20 7.3.1 Transmit Function......................................... 20 7.3.2 Receive Function .......................................... 21 7.3.3 Link Monitor................................................. 21 7.3.4 Jabber............................................................ 21 7.3.5 Loopback ...................................................... 21 7.4 100Base-TX ......................................................... 21 7.4.1 Transmit Function......................................... 21 7.4.2 Receive Function .......................................... 21 7.4.3 Link Monitor................................................. 22 7.4.4 Baseline Wander Compensation ................... 23 7.5 100Base-FX ......................................................... 23 7.5.1 Transmit Function......................................... 23 7.5.2 Receive Function .......................................... 23 7.5.3 Link Monitor ................................................ 24 7.5.4 Far-End-Fault-Indication (FEFI) .................. 24 7.5.5 Reduced Fiber Interface............................... 24 7.6 RMII/SMII/SS-SMII ............................................ 24 7.6.1 RMII (Reduced MII) .................................... 25 7.6.2 SMII (Serial MII) ......................................... 25 7.5.3 SS-SMII (Source Synchronous -Serial MII)....... 27 7.7 Power Saving and Power Down Mode ................ 28 7.7.1 Power Saving Mode ..................................... 28 7.7.2 Power Down Mode....................................... 28 7.8 LED Configuration .............................................. 28 7.8.1 LED Blinking Time ...................................... 28 7.8.2 Serial Stream Order ...................................... 29 7.8.3 Bi-Color LED ............................................... 30 7.9 Crossover Detection and Auto Correction........... 30 7.10 Polarity Detection and Auto Correction ............ 31 7.11 2.5V Power Generation ..................................... 31 8. Design and Layout Guide ......................................... 32 8.1 General Guidelines............................................... 32 8.2 Differential Signal Layout Guidelines ................. 32 8.3 Clock Circuit ........................................................ 32 8.4 2.5V power........................................................... 32 8.5 Power Planes ........................................................ 32 8.6 Ground Planes ...................................................... 32 8.7 Transformer Options ............................................ 32 9. Application information ........................................... 33 9.1 10Base-T/100Base-TX Application ..................... 33 9.2 100Base-FX Application...................................... 34 10. Electrical Characteristics ....................................... 35 10.1 Absolute Maximum Ratings............................... 35 10.2 Operating Range ................................................ 35 10.3 DC Characteristics ............................................. 35 10.4 AC Characteristics.............................................. 36 10.5 Digital Timing Characteristics ........................... 37 10.6 Thermal Data...................................................... 38 11. Mechanical Dimensions .......................................... 39 2003/04/04 1 Rev.1.97 RTL8208 1. Features Supports 8-port integrated physical layer and transceiver for 10Base-T and 100Base-TX Up to 8 ports support of 100Base-FX Reduced 100Base-FX interface (patented) Robust baseline wander correction for improved 100BASE-TX performance Fully compliant with IEEE 802.3/802.3u IEEE 802.3u compliant Auto-negotiation for 10/100 Mbps control Hardware controlled Flow control advertisement ability Supports RMII/SMII/SS-SMII interfaces Multiple driving capabilities of RMII/SMII/SS-SMII Supports 25MHz crystal as clock source for RMII with 50MHz REFCLK output for MAC Very low power consumption Supports port-pair loop mode (PP-LPBK mode) Supports two Power reduction methods: 1. Power saving mode (cable detection) 2. Power down mode Power-on auto reset function eliminates the need for external reset circuits Crossover detection and auto correction. Flexible LED display modes through 2-wire serial LED control interface 128-pin PQFP 2.5V/3.3V power supply 0.25m, CMOS technology 2. General Description The RTL8208 is a highly integrated 8 port, 10Base-T/100Base-TX/FX, Ethernet transceiver implemented in 0.25m CMOS technology. It is currently the world's smallest Octal-PHY chip package with many special patented features. Traditional SD pins in 100Base-FX are omitted by Realtek patent to obtain fewer pin-count. Flexible hardware settings are provided to configure the various operating modes of the chip. The RTL8208 consists of 8 separate and independent channels. Each channel consists of an RMII/SMII/SS-SMII interface to MAC controller, and hardware pins are used to configure the interface for RMII, or SMII, or SS-SMII mode. In RMII mode, another hardware pin is used to set port-pair loop mode (PP-LPBK mode), which can extend physical transmission length or perform physical media transport operations without any switch controller. In addition, the RTL8208 features very low power consumption, as low as 1.8 W (max.). Additionally, pin-outs are designed to provide optimized direct routing can be implemented, which simplifies the layout work and reduces EMI noise issues. 2003/04/04 2 Rev.1.97 RTL8208 3. Block Diagram RXCL K FX input SYNC EESCRAMBLE R RX FIFO MODE[1:0] RXD0 RXD1 CRSD V RMII RX CR S RXD V R STAT X E MACHIN E RX RECEIVER TX+/- BYP-DE SC R CLOCK RECOVERY ADAPTIVE EQUALIZER RXD[3:0 ] 4B/5 DECOD B E SERIAL-TO-PAR ALLE L SMII RX TP input RX+/- SMII TX CO TXCL L TXE K TXE N R T STAT X MACHIN E E FX enable TX/FX output SCAMBLE R 4B/5B ENCODER TXD[3:0 ] PARALLEL-TO-SERIA L TXD0 TXD1 TXE N RMII TX BYP-SC R MLT ENCODE 3 R 10/100 TX/FX DRIVE R TX TRANSMITTER 2003/04/04 3 Rev.1.97 2003/04/04 CRS_DV[0] TX_EN[0] TXON[1] VDDAH RXD0[0] RXD1[0] TXD0[0] TXD1[0] TXON[0] TXOP[0] VDDAH VDDAH VCTRL VDDAL RXIN[0] RXIP[0] MDIO IBREF MDC VSSA VDD VSS VSS X2 X1 103 126 124 123 122 121 120 119 118 117 116 115 114 125 113 112 111 110 109 108 107 106 105 104 127 TXOP[1] 128 1 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 66 65 TXD0[1] TXD1[1] CRS_DV[1] RXD0[1] RXD1[1] TX_EN[2] TXD0[2] TXD1[2] CRS_DV[2] RXD0[2] RXD1[2] VSS VDD TX_EN[3] TXD0[3] TXD1[3] CRS_DV[3] RXD0[3] RXD1[3] VSS RX_SYNC TX_SYNC VDD TX_EN[4] TXD0[4] TXD1[4] CRS_DV[4] RXD0[4] RXD1[4] VSS VDD TX_EN[5] TXD0[5] TXD1[5] CRS_DV[5] RXD0[5] RXD1[5] 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 VSSA RXIP[1] RXIN[1] VDDAL VDDAL RXIN[2] RXIP[2] VSSA TXOP[2] TXON[2] VDDAH VDDAH TXON[3] TXOP[3] VSSA RXIP[3] RXIN[3] VDDAL VDDAL RXIN[4] RXIP[4] VSSA TXOP[4] TXON[4] VDDAH VDDAH TXON[5] TXOP[5] VSSA RXIP[5] RXIN[5] VDDAL VDDAL RXIN[6] RXIP[6] VSSA TXOP[6] TXON[6] TX_EN[1] 4. Pin Assignments RTL8208 08042T1 050A TAIWAN 4 VSSA VDDAL RXIP[7] RXIN[7] VDDAH VDDAH TXD1[7] RXD1[7] RXD0[7] TXOP[7] TXON[7] RESET# REFCLK LED_CLK LED_DATA CRS_DV[7] VSS VDD TXD0[7] TX_EN[7] TXD1[6] TXD0[6] RXD1[6] RXD0[6] TX_EN[6] CRS_DV[6] RTL8208 Rev.1.97 RTL8208 'I' stands for input; 'O' stands for output; 'A' stands for analog; `D' stands for digital Pin Name VSSA RXIP[1] RXIN[1] VDDAL VDDAL RXIN[2] RXIP[2] VSSA TXOP[2] TXON[2] VDDAH VDDAH TXON[3] TXOP[3] VSSA RXIP[3] RXIN[3] VDDAL VDDAL RXIN[4] RXIP[4] VSSA TXOP[4] TXON[4] VDDAH VDDAH TXON[5] TXOP[5] VSSA RXIP[5] RXIN[5] VDDAL VDDAL RXIN[6] RXIP[6] VSSA TXOP[6] TXON[6] VDDAH VDDAH TXON[7] TXOP[7] VSSA RXIP[7] RXIN[7] VDDAL RESET# REFCLK LED_DATA/LEDMODE[1] LED_CLK/LEDMODE[0] RXD1[7]/EN_AUTOXOVER RXD0[7]/DRIVE[0] CRS_DV[7]/MODE[0] TXD1[7] TXD0[7] TX_EN[7] VDD VSS RXD1[6]/DISBLINK RXD0[6]/DRIVE[1] CRS_DV[6]/MODE[1] TXD1[6] TXD0[6] TX_EN[6] Pin# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Type AGND AI AI AVDD AVDD AI AI AGND AO AO AVDD AVDD AO AO AGND AI AI AVDD AVDD AI AI AGND AO AO AVDD AVDD AO AO AGND AI AI AVDD AVDD AI AI AGND AO AO AVDD AVDD AO AO AGND AI AI AVDD I I/O I/O I/O I/O I/O I/O I I I DVDD DGND I/O I/O I/O I I I Pin Name RXD1[5]/LED_BLNK_TIME RXD0[5] CRS_DV[5]/TP_PAUSE TXD1[5] TXD0[5] TX_EN[5] VDD VSS RXD1[4]/PHY_ADDR[4] RXD0[4] CRS_DV[4]/RX_CLK TXD1[4] TXD0[4] TX_EN[4]/TX_CLK VDD SYNC/TX_SYNC RX_SYNC/RPT_MODE VSS RXD1[3]/PHY_ADDR[3] RXD0[3] CRS_DV[3]/FX_PAUSE TXD1[3] TXD0[3] TX_EN[3] VDD VSS RXD1[2]/TEST RXD0[2] CRS_DV[2]/FX_DUPLEX TXD1[2] TXD0[2] TX_EN[2] RXD1[1] RXD0[1] CRS_DV[1]/SEL_TXFX[1] TXD1[1] TXD0[1] TX_EN[1] VDD VSS RXD1[0] RXD0[0] CRS_DV[0]/SEL_TXFX[0] TXD1[0] TXD0[0] TX_EN[0] VSS MDIO MDC X1 X2 VCTRL VDDAH IBREF VDDAL RXIN[0] RXIP[0] VSSA TXOP[0] TXON[0] VDDAH VDDAH TXON[1] TXOP[1] Pin# 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 Type I/O O I/O I I I DVDD DGND I/O O O I I I DVDD I I/O DGND I/O O I/O I I I DVDD DGND I/O O I/O I I I O O I/O I I I DVDD DGND O O I/O I I I DGND I/O I I O I/O AVDD AO AVDD AI AI AGND AO AO AVDD AVDD AO AO 2003/04/04 5 Rev.1.97 RTL8208 5. Pin Description In order to reduce pin count, and therefore size and cost, some pins have multiple functions. In those cases, the functions are separated with a "/" symbol. Refer to the Pin Assignment diagram for a graphical representation. 'I' stands for input 'O' stands for output 'A' stands for analog signal 'D' stands for digital signal 'P' stands for power 'G' stands for ground 'Pu' stand for internal pull up (75K ohm) 'Pd' stand for internal pull down (75K ohm) 5.1 Media Connection Pins Pin Name RXIP[7:0] RXIN[7:0] TXOP[7:0] TXON[7:0] Pin 44,35,30,21,16, 7,2,121 45,34,31,20,17, 6,3,120 42,37,28,23,14, 9,128,123 41,38,27,24, 13,10,127,124 Type AI AI AO AO Description Receiver Input: Differential positive signal shared by 100Base-TX, 100Base-FX, 10Base-T. Receiver Input: Differential negative signal shared by 100Base-TX, 100Base-FX, 10Base-T. Transmitter Output: Differential positive signal shared by 100Base-TX, 100Base-FX, 10Base-T. Transmitter Output: Differential negative signal shared by 100Base-TX, 100Base-FX, 10Base-T. 5.2 Power and Ground Pins Pin Name VDDAH VDDAH VDDAL VSSA VDD VSS Pin 117 11,12,25,26,39, 40,125,126 119,4,5,18,19, 32,33,46 122,1,8,15,22, 29,36,43 57,71,79,89, 103 58,72,82,90, 104,111 Type P P P G P G Description Power for IBREF 3.3V Power to analog: Used for transmitters and equalizers. 2.5V Power to analog: Used for PLL circuits. Analog ground Digital 2.5V power supply Digital ground 2003/04/04 6 Rev.1.97 RTL8208 5.3 Miscellaneous Pins Pin Name RESET# X1 X2 REFCLK Pin 47 114 115 48 Type I, (Pu) I O I/O Description Reset: This is an active low input. To complete the reset function, this pin must be asserted low for at least 10ms. 25MHz Crystal X1 or 25MHz Oscillator clock input: When X1 is pulled low, X2 must be floating. REFCLK will then be the chip clock input. 25MHz Crystal X2 Reference clock: If X1 is 25MHz active, REFCLK is a 50MHz output. If X1 is pulled-low (disabled), REFCLK is the clock input as below: 50MHz 100ppm clock input for RMII mode. 125MHz 100ppm clock input for SMII/SS-SMII mode. Reference Bias Resistor: This pin must be tied to analog ground through an external 1.96K resistor when using a 1:1 transformer on Tx/Rx. Voltage control: This pin controls a PNP transistor to generate the 2.5V power supply for VDD and VDDAL pins. IBREF VCTRL 118 116 A O 2003/04/04 7 Rev.1.97 RTL8208 5.4 RMII/SMII/SS-SMII Pins Pin Name TXD0[7:0] Pin 55,63,69,77, 87,95,101,109 Type I Description Transmit Data Input (bit 0): In RMII, TXD0 and TXD1 are the di-bits input transmitted and driven synchronously to REFCLK from MAC. In SMII, TXD0 inputs the data that is transmitted and is driven synchronously to REFCLK. In 100Mbps, TXD0 inputs a new 10-bit segment starting with SYNC. In 10Mbps, TXD0 must repeat each 10-bit segment 10 times. In SS-SMII, TXD0 behaves as SMII except synchronous to TX_CLK instead of REFCLK and 10-bit segment starting with TX_SYNC instead of SYNC. Transmit Data Input (bit 1): In RMII, TXD1 and TXD0 are the input di-bits synchronously to REFCLK. In SMII/SS-SMII, TXD1 is not used and should be tied either high or low. Transmit Enable: In RMII , TX_EN indicates the di-bits on TXD is valid and is synchronous to REFCLK. In SMII/SS-SMII, TX_EN[7:0] are not used. Receive Data Input (bit 0): In RMII, RXD0 and RXD1 output di-bits synchronously to REFCLK. In SMII, RXD0 outputs data or inband management information synchronously to REFCLK. In 100Mbps, RXD0 outputs a new 10-bit segment starting with SYNC. In 10Mbps, RXD0 must repeat each 10-bit segment 10 times. In SS-SMII, RXD0 behaves as SMII except synchronous to RX_CLK instead of REFCLK and 10-bit segment starting with RX_SYNC instead of SYNC. Receive Data Input (bit 1): In RMII, RXD1 and RXD0 output di-bits synchronously to REFCLK. In SMII/SS-SMII, RXD1is not used and they are driven low. Carrier Sense and Data Valid: In RMII, CRS_DV is asynchronous to REFCLK and asserts when the medium is non-idle. In SMII/SS-SMII, CRS_DV[7:0] are not used and driven low. Receive Clock: In SS-SMII, CRS_DV[4] of RMII is used as RX_CLK, which is a 125MHz clock output. Receive Synchronous : In SS-SMII, RX_SYNC is a sync signal used to delimit the 10-bit segment of RXD0 for all ports. Sync/Transmit Synchronous: In SMII, SYNC is a sync signal used to delimit a 10-bit segment of RXD0 and TXD0 for all ports. In SS-SMII, TX_SYNC is a sync signal used to delimit the 10-bit segment of TXD0 for all ports. Transmit Clock/Transmit Enable: In SS-SMII, TX_EN[4] of RMII is used as TX_CLK, which is a 125MHz clock input from MAC. TXD1[7:0] 54,62,68,76, 86,94,100,108 I TX_EN [7:0] 56,64,70,78, 88,96,102,110 52,60,66,74, 84,92,98,106 I RXD0[7:0] O RXD1[7:0] CRS_DV[7:0] 51,59,65,73, 83,91,97,105 53,61,67,75, 85,93,99,107 75 81 O O RX_CLK/ CRS_DV[4] RX_SYNC O I/O SYNC/ TX_SYNC TX_CLK/ TX_EN[4] 80 I 78 I 2003/04/04 8 Rev.1.97 RTL8208 5.5 SMI (Serial Management Interface) Pins Pin Name MDIO Pin 112 Type I/O, (Pu) Description Management Data I/O. Bi-directional data interface. A 1.5K pull-up resistor is required (as specified in IEEE802.3u). The MAC controller access of the MII registers should be delayed at least 700us after completion of the reset because of the internal reset operation of the RTL8208 Management Data Clock. 0 to 25MHz clock sourced by MAC to sample MDIO. The MAC controller access of the MII registers should be delayed at least 700us after completion of the reset because of the internal reset operation of the RTL8208 MDC 113 I, (Pd) 5.6 LED Pins Pin Name LED_DATA/ LEDMODE[1] Pin 49 Type I/O Description LED_DATA outputs serial status bits that can be shifted into a shift register to be displayed via LEDs. LED_DATA is output synchronously to LED_CLK. This pin is latched upon reset as LEDMODE[1] LEDMODE[1:0] controls the forms of serial LED statuses. See LED operation mode section. LED_CLK outputs the reference clock for the serial LED signals. This pin is latched upon reset as LEDMODE[0] LED_CLK/ LEDMODE[0] 50 I/O 2003/04/04 9 Rev.1.97 RTL8208 5.7 Mode Control Pins Pin Name SEL_TXFX[1:0]/ CRS_DV[1:0] Pin 99,107 Type Description I/O, Select 10/100BaseTX or 100BaseFX: (default = 2'b00) (Pd,Pd) If RPT_MODE = 0: 2'b00: All 8 ports (port0~port7) are 10Base-T/100Base-TX. 2'b01: Port 7 is 100FX, other ports are 10Base-T/100Base-TX. 2'b10: Ports 6 & 7 are 100FX, other ports are 10Base-T/100Base-TX. 2'b11: All 8 ports are 100Base-FX. If RPT_MODE =1: 2'b00: All 8 ports (port0~port7) are 10Base-T/100Base-TX. 2'b01: Port 7 and 5 are 100FX, others are 10Base-T/100Base-TX. 2'b10: Ports 1,3,5&7 are 100FX, others are 10Base-T/100Base-TX. 2'b11: All 8 ports are 100Base-FX. I/O, Port Pair Loop Back mode: (default =0) (Pd) Upon power-on reset, this pin is input to assert PP-LPBK mode. When set, all eight ports are port-pair looped back, acting like a signal regeneration/transformation repeater. Refer to the section covering PP-LPBK mode. I/O, PHY Address: (default = 2'b01) These 2bits determine the highest (Pd,Pu) 2bits of 5-bit PHY address upon reset. I/O, Select RMII/SMII/SS-SMII mode: (default = 2'b11) (Pu,Pu) 2'b1x: RMII 2'b00: SMII 2'b01: SS-SMII I/O, Twisted Pair Pause capability: (default =1) Sets the Flow control (Pu) ability of Reg.4.10 for UTP ports upon power-on reset. 1: With flow control ability. 0: Without flow control ability I/O, 100Base-FX Flow control capability: (default =1) Forces the flow (Pu) control capability of Reg.4.10 and Reg.5.10 upon power-on reset. 1: With flow control ability in 100Base-FX. 0: Without flow control ability in 100Base-FX. I/O, FX_DUPLEX: Force 100Base-FX Full Duplex Mode: (default =1) (Pu) This pin sets 100Base-FX duplex and affects those ports in 100Base-FX mode. 1=full duplex, 0=half duplex. Upon reset, this pin sets the default values of Reg.0.8 of those ports in 100Base-FX. I/O, Enable Auto Crossover Detection: (default =1) (Pu) 1: Enable auto crossover detection 0: Disable auto crossover detection I/O, Disable power-on reset LEDs blinking: (default = 0) (Pd) 1=Disable power-on LED blinking 0=blink. I/O, LED blink time: (default =1) Used to control blinking speed of (Pu) activity and collision LEDs. 1= 43ms 0= 120ms I, LEDMODE[1:0]: (default = 00) Controls the forms of serial LED status. (Pd,Pd) LEDMODE Mode Output 2'b00 3-bit serial stream Col/Fulldup, Link/Act, Spd 2'b01 2-bit serial stream Spd, Link/Act 2'b10 3-bit for Bi-color LED Col/Fulldup, Link/Act, Spd See LED operation mode section for more information. 2003/04/04 10 Rev.1.97 PP-LPBK mode / RX_SYNC 81 PHY_ADDR[4:3]/ RXD1[4:3] MODE[1:0]/ CRS_DV[6:7] TP_PAUSE/ CRS_DV[5] FX_PAUSE/ CRS_DV[3] FX_DUPLEX/ CRS_DV[2] 73,83 61,53 67 85 93 EN_AUTOXOVER /RXD1[7] DISBLINK/ RXD1[6] LED_BLNK_TIME/ RXD1[5] LEDMODE[1:0] 51 59 65 49,50 RTL8208 Pin Name DRIVE[0]/ RXD0[7] DRIVE[1]/ RXD0[6] Pin 52 60 Description DRIVE[0]: Controls the output driving ability of SSMII RX_CLK. 1'b0: 12mA (default) 1'b1: 16mA I/O, DRIVE[1]: Controls the output driving abilities of the (Pd,Pd) RMII/SMII/SS-SMII signals other than RX_CLK. Drive [1:0] 2'b00 2'b01 2'b10 2'b11 Output driving ability 4mA (default) 8mA 12mA 16mA Type I/O, (Pd) 5.8 Reserved Pins Pin Name ENANAPAR/ RXD1[1] TEST/ RXD1[2] CPRST/ RXD1[0] Pin 97 91 105 Type I/O, (Pd) I/O, (Pd) I/O, (Pd) Description Reserved for internal use. Must be kept floating. TEST. Reserved for internal use. Must be kept floating. Reserved for internal use. Must be kept floating. 2003/04/04 11 Rev.1.97 RTL8208 6. Register Descriptions The first six registers of the MII are defined by the MII specification. Other registers are defined by Realtek Semiconductor Corp. for internal use and are reserved for specific uses. Register Description Default 0 Control Register 3100 1 Status Register 0F49 2 PHY Identifier 1 Register 001C 3 PHY Identifier 2 Register C883 4 Auto-Negotiation Advertisement Register 05E1 5 Auto-Negotiation Link Partner Ability Register 0001 6 Auto-Negotiation Expansion Register 0000 RO: Read Only RW: Read/Write LL: Latch Low until cleared LH: Latch High until cleared SC: Self Clearing 6.1 Register0: Control Reg. bit 0.15 0.14 Name Reset Loopback Description 1=PHY reset. This bit is self-clearing. This will loopback TXD to RXD and ignore all the activities on the cable media. Valid only for 10Base-T. 1=Enable loopback. 0=Normal operation. When Nway is enabled, this bit reflects the result of Auto-negotiation. (Read only) When Nway is disabled, this bit can be set by SMI*. (Read/Write) When 100FX is enabled, this bit =1 (Read only) 1=100Mbps. 0=10Mbps. This bit can be set through SMI.(Read/Write) When 100FX is enabled, this bit =0 (Read only) 1 = Enable Auto-negotiation process. 0 = disable Auto-negotiation process. 1=Power down. All functions will be disabled except SMI.read/write function. 0=Normal operation. 1 = Electrically isolate the PHY from RMII/SMII/SS-SMII. PHY is still able to respond to MDC/MDIO. 0 = Normal operation 1=Restart Auto-Negotiation process. 0=Normal operation. When Nway is enabled, this bit reflects the result of Auto-negotiation. (Read only) When Nway is disabled, this bit can be set by SMI*. (Read/Write) When 100FX is enabled, this bit is determined by the FX_DUPLEX pin. (Read/Write) 1=Full duplex operation. 0=Half duplex operation. Mode RW/SC RW Default 0 0 0.13 Spd_Sel RW 1 0.12 Auto Negotiation Enable Power Down Isolate Restart Auto Negotiation Duplex Mode RW 1 or 0 for 100FX 0 0 0 1 0.11 0.10 0.9 0.8 RW RW RW/SC RW 0.[7:0] Reserved 0 *SMI: Serial Management Interface , which is composed of MDC,MDIO, allows MAC to manage PHY. 2003/04/04 12 Rev.1.97 RTL8208 Reset - In order to reset the RTL8208 by software control, a `1' must be written to bit 15 using an SMI write operation. The bit clears itself after the reset process is complete, and does not need to be cleared using a second SMI write. Writes to other Control register bits will have no effect until the reset process is completed, which requires approximately 1us. Writing a `0' to this bit has no effect. Because this bit is self clearing after a few cycles from a write operation, it will return a `0' when read. Loopback - The RTL8208 may be placed into loopback mode by writing a `1' to bit 14. Loopback mode may be cleared either by writing a `0' to bit 14 or by resetting the chip. When this bit is read, it will return a `1' when the chip is in software-controlled loopback mode, otherwise it will return a `0'. Speed Selection - If Auto-negotiation is enabled, this bit has no effect on the speed selection. However, if Auto-negotiation is disabled by software control, the operating speed of the RTL8208 can be forced by writing the appropriate value to bit 13. Writing a `1' to this bit forces 100Base-X operation, while writing a `0' forces 10Base-T operation. When this bit is read, it returns the value of the software controlled forced speed selection only. Auto Negotiation Enable - Default Auto Negotiation enable for all TP ports and disable for FX ports. Auto-negotiation can be disabled by either software control to set 0.12=0. Power Down - The RTL8208 supports a low power mode which is intended to decrease power consumption. Writing a `1' will enable power down mode, and writing a `0' will return the RTL8208 to normal operation. When read, this register will return a `1' when in power down mode, and a `0' during normal operation. Isolate - Each individual PHY may be isolated from its MII by writing a `1' to bit 10. All MII outputs will be tri-stated and all MII inputs will be ignored. Since the MII management interface is still active, the isolate mode may be cleared either by writing a `0' to bit 10 or by resetting the chip. When this bit is read, it will return a `1' when the chip is in isolate mode, and a `0' during normal operation. Restart Auto Negotiation - Bit 9 is a self-clearing bit that allows the Auto-negotiation process to be restarted, regardless of the current status of the Auto-negotiation state machine. In order for this bit to have an effect, Auto-negotiation must be enabled. Writing a `1' to this bit restarts Auto-negotiation while writing a `0' to this bit has no effect. When this bit is read, it will always return a `0'. Duplex Mode - By default, the RTL8208 powers up in half duplex mode. The chip can be forced into full duplex mode by writing a `1' to bit 8 while Auto-negotiation is disabled. Half duplex mode can be resumed either by writing a `0' to bit 8 or by resetting the chip. When Nway is enabled, this bit reflects the results of the Auto-negotiation, and is in a read only mode. When Nway is disabled, this bit can be set through the SMI, and is in a read/write mode. When 100FX is enabled, this bit can be set through the SMI or FX_DUPLEX pin and is in a read/write mode. Reserved Bits - All reserved MII register bits must be written as `0' at all times. Ignore the RTL8208 output when these bits are read. 2003/04/04 13 Rev.1.97 RTL8208 6.2 Register1: Status Reg. bit 1.15 1.14 1.13 1.12 1.11 1.[10:7] 1.6 1.5 1.4 Name 100Base_T4 100Base_TX_FD 100Base_TX_HD 10Base_T_FD 10Base_T_HD Reserved MF Preamble Suppression Auto-negotiate Complete Remote Fault Description 0 = no 100Base-T4 capability. 1=100Base-TX full duplex capable. 0=Not 100Base-TX full duplex capable. 1=100Base-TX half duplex capable. 0=Not 100Base-TX half duplex capable. 1=10Base-TX full duplex capable. 0=Not 10Base-TX full duplex capable. 1=10Base-TX half duplex capable. 0=Not 10Base-TX half duplex capable. The RTL8208 will accept management frames with preamble suppressed. 1=Auto-negotiation process completed. Reg.4,5 are valid if this bit is set. 0=Auto-negotiation process not completed. 1=Remote fault indication from link partner has been detected. 0=No remote fault indication detected. When in 100FX mode, this bit means in-band signal Far-End-Fault is detected. Refer to FX MODE section. 1=Nway Auto-negotiation capable. (permanently =1) 0=Without Nway Auto-negotiation capability. 1=Link has never failed since previous read. 0=Link has failed since previous read. If link fails, this bit will be set to 0 until bit is read. 1=Jabber detected. 0=No Jabber detected. The jabber function is disabled in 100Base-X mode. Jabber is supported only in 10Base-T mode. 1=Extended register capable. (permanently =1) 0=Not extended register capable. Mode RO RO RO RO RO RO RO RO RO/LH Default 0 1 1 1 1 0 1 0 0 1.3 1.2 1.1 Auto-Negotiation Ability Link Status Jabber Detect RO RO/LL RO/LH 1 0 0 1.0 Extended Capability RO 1 100Base_T4 - The RTL8208 does not support the T4 function. Any reads to this bit will return a `0'. 100Base_TX_FD - The RTL8208 is capable of operating in 100Base-TX full duplex mode. 100Base_TX_HD - The RTL8208 is capable of operating in 100Base-TX half duplex mode. 10Base_T_FD - The RTL8208 is capable of operating in 10Base-T full duplex mode. 10Base_T_HD - The RTL8208 is capable of operating in 10Base-T half duplex mode. Reserved - Ignore the output of the RTL8208 when these bits are read. MF Preamble Suppression - Management Frame Preamble Suppression is permanently set in the RTL8208, allowing subsequent MII management frames to be accepted with or without the standard preamble pattern. Only two preamble bits are required between successive management commands, instead of the normal 32, however, a minimum of 32 preamble bits are required for the first SMI read/write transaction after reset. One idle bit is required between any two management transactions (as defined in IEEE802.3u spec). Reads of this bit will always return a `1'. Auto-negotiate Complete - Bit 5 will return a `1' if the Auto-negotiation process has been completed and the contents of registers 4 and 5 are valid. Remote Fault - When link partner detect far-end fault, it would send far-end indication stream pattern. When RTL8208 receive this pattern, set Reg1.4=1. Auto-Negotiation Ability - The RTL8208 is capable of performing IEEE Auto-negotiation, and will return a `1' when bit 4 is read, regardless of whether or not the Auto-negotiation function has been disabled. Link Status - The RTL8208 will return a `1' on bit 2 when the link state machine is in Link Pass, indicating that a valid link has been established. Otherwise, it will return `0'. When a link failure occurs after the link pass state has been entered, the Link 2003/04/04 14 Rev.1.97 RTL8208 Status bit will be latched at `0' and will remain so until the bit is read. After the bit is read, it becomes `1' if the Link Pass state has been entered again. Jabber Detect - The RTL8208 will return a `1' on bit 1 if a jabber condition has been detected. After the bit is read, or if the chip is reset, it reverts to `0'. This is for 10Base-T only. Jabber occurs when a predefined excessive long packet is detected for 10Base-T. When the duration of TX_EN exceeds the jabber timer (21ms), the transmit and loopback functions will be disabled and the COL LED starts blinking. After TX_EN goes low for more than 500 ms, the transmitter will be re-enabled and the COL LED stops blinking. Extended Capability - The RTL8208 supports extended capability registers, and will return a `1' when bit 0 is read. Several extended registers have been implemented in the RTL8208. 6.3 Register2: PHY Identifier 1 Register The PHY Identifier Registers #1 and #2 together form a unique identifier for the PHY section of this device. The Identifier consists of a concatenation of the Organizationally Unique Identifier (OUI), the vendor's model number and the model revision number. A PHY may return a value of zero in each of the 32 bits of the PHY Identifier if desired. The PHY Identifier is intended to support network management. Reg. bit 2.[15:0] Name OUI Description Composed of the 3rd to 18th bits of the Organizationally Unique Identifier (OUI), respectively. Mode RO Default 001C h 6.4 Register3: PHY Identifier 2 Register Reg. bit 3.[15:10] 3.[9:4] 3.[3:0] Name OUI Model Number Revision Number Description Assigned to the 19th through 24th bits of the OUI. Manufacturer's model number 08. Manufacturer's revision number 03. Mode RO RO RO Default 110010 001000 0011 2003/04/04 15 Rev.1.97 RTL8208 6.5 Register4: Auto-Negotiation Advertisement This register contains the advertisement abilities of this device as they will be transmitted to its Link Partner during Auto-negotiation. Reg. bit Name Description Mode Default 4.15 Next Page 1=Next Page enabled. RO 0 0=Next Page disabled. (Permanently =0) 4.14 Acknowledge Permanently =0. RO 0 4.13 Remote Fault 1=Advertises that RTL8208 has detected a remote fault. RW 0 0=No remote fault detected. 4.[12:11] Reserved RO 0 4.10 Pause 1=Advertises that the RTL8208 has flow control capability. RW Set by 0=Without flow control capability. TP_PAUSE In 100FX mode, this bit is set by 100FX_PAUSE upon reset. Or In 100/10TP mode, this bit is set by TP_PAUSE upon reset. FX_PAUSE 4.9 100Base-T4 1 = 100Base-T4 capable. RO 0 0 = Not 100Base-T4 capable. (Permanently =0) 4.8 100Base-TX-FD 1=100Base-TX full duplex capable. RW 1 0=Not 100Base-TX full duplex capable. 4.7 100Base-TX 1=100Base-TX half duplex capable. RW 1 0=Not 100Base-TX half duplex capable. 4.6 10Base-T-FD 1=10Base-TX full duplex capable. RW 1 0=Not 10Base-TX full duplex capable. 4.5 10Base-T 1=10Base-TX half duplex capable. RW 1 0=Not 10Base-TX half duplex capable. 4.[4:0] Selector Field [00001]=IEEE802.3 RO 00001 Next Page - The RTL8208 does not implement the Next Page function, so bit 15 will always return a `0' when read. Acknowledge - Because the Next Page function is not implemented, bit 14 will always return a `0' when read. Remote Fault - When RTL8208 can not receive valid signal , set Reg4.13=1. The RTL8208 advertises this information to inform link partner. Reserved - Ignore the output of the RTL8208 when these bits are read. Pause -Setting this bit indicates the availability of Flow Control capabilities when full duplex operation is in use. This bit is used by one MAC to communicate Pause Capability to its Link Partner and has no effect on PHY operation. 100Base-T4 - Because the RTL8208 does not support the T4 function, any reads to this bit will return a `0'. 100Base-TX-FD - This bit advertises the ability to the Link Partner that the RTL8208 can operate in 100Base-TX full duplex mode. Writing a `0' to this bit will suppress the transmission of this ability to the Link Partner. Resetting the chip will restore the default value. The default value is `1' and writing a `1' will set this bit to `1'. Reading this bit will return the last written value or the default value if no write has been completed since the last reset. 100Base-TX - This bit advertises the ability to the Link Partner that the RTL8208 can operate in 100Base-TX half duplex mode. Writing a `0' to this bit will suppress the transmission of this ability to the Link Partner. Resetting the chip will restore the default value. The default value is `1' and writing a `1' will set this bit to `1'. Reading this bit will return the last written value or the default value if no write has been completed since the last reset. 10Base-T-FD - This bit advertises the ability to the Link Partner that the RTL8208 can operate in 10Base-T full duplex mode. Writing a `0' to this bit will suppress the transmission of this ability to the Link Partner. Resetting the chip will restore the default value. The default value is `1' and writing a `1' will set this bit to `1'. Reading this bit will return the last written value or the default value if no write has been completed since the last reset. 10Base-T - This bit advertises the ability to the Link Partner that the RTL8208 can operate in 10Base-T half duplex mode. Writing a `0' to this bit will suppress the transmission of this ability to the Link Partner. Resetting the chip will restore the default value. The default value is `1' and writing a `1' will set this bit to `1'. Reading this bit will return the last written value or the default value if no write has been completed since the last reset. Selector Field - Bits 4:0 contain a fixed value of 00001, indicating that the chip belongs to the 802.3 class of PHY transceivers. 2003/04/04 16 Rev.1.97 RTL8208 6.6 Register5: Auto-Negotiation Link Partner Ability This register contains the advertised abilities of the Link Partner as received during Auto-negotiation. The content changes after the successful Auto-negotiation. Reg. bit Name Description Mode Default 5.15 Next Page 1=Link partner desires Next Page transfer. RO 0 0=Link partner does not desire Next Page transfer. 5.14 Acknowledge 1=Link Partner acknowledges reception of FLP words. RO 0 0=No acknowledgement by Link Partner. 5.13 Remote Fault 1=Remote Fault indicated by Link Partner. RO 0 0=No remote fault indicated by Link Partner. 5.12-11 Reserved RO 0 5.10 Pause 1=Flow control supported by Link Partner. RW 0 0=No flow control supported by Link Partner. When Nway is enabled, this bit reflects Link Partner ability. (read only) In 100FX mode, this bit is set by FX_PAUSE or SMI. 5.9 100Base-T4 1=100Base-T4 supported by Link Partner. RO 0 0=100Base-T4 not supported by Link Partner. 5.8 100Base-TX-FD 1=100Base-TX full duplex supported by Link Partner. RO 0 0=100Base-TX full duplex not supported by Link Partner. For 100FX mode, this bit is set when Reg.0.8=1 or FX_DUPLEX =1. When Nway is disabled, this bit is set when Reg.0.13=1 and Reg.0.8=1. 5.7 100Base-TX 1=100Base-TX half duplex supported by Link Partner. RO 0 0=100Base-TX half duplex not supported by Link Partner. For 100FX mode, this bit is set when Reg.0.8=0 or FX_DUPLEX =0. When Nway is disabled, this bit is set when Reg.0.13=1 and Reg.0.8=0. 5.6 10Base-T-FD 1=10Base-TX full duplex supported by Link Partner. RO 0 0=10Base-TX full duplex not supported by Link Partner. When Nway is disabled, this bit is set when Reg.0.13=0 and Reg.0.8=1. 5.5 10Base-T 1=10Base-TX half duplex supported by Link Partner. RO 0 0=10Base-TX half duplex not supported by Link Partner. When Nway disabled, this bit is set when Reg.0.13=0,and Reg.0.8=0. 5.[4:0] Selector Field [00001]=IEEE802.3 RO 00001 Note that the values are only guaranteed to be valid once Auto-negotiation has successfully completed, as indicated by bit 5 of the MII Status Register. Next Page - Bit 15 returns a value of `1' when the Link Partner implements the Next Page function and has Next Page information that it wants to transmit. However, since the RTL8208 does not implement the Next Page function, it ignores the Next Page bit, except to copy it to this register. Acknowledge - Bit 14 is used by Auto-negotiation to indicate that a device has successfully received its Link Partner's Link Code Word. Remote Fault - Bit 13 returns a value of `1' when the Link Partner signals that it has detected a remote fault. The RTL8208 advertises this information, but does not act upon it. Reserved - Ignore the output of the RTL8208 when these bits are read. Pause - Indicates that the Link Partner pause bit is set. 100Base-T4 - Though the RTL8208 does not support the T4 function, this bit reflects this ability of the Link Partner. 100Base-TX-FD - This bit indicates that the Link Partner can support 100Base-TX full duplex mode. This bit is cleared any time Auto-negotiation is restarted or the RTL8208 is reset. 100Base-TX - This bit indicates that the Link Partner can support 100Base-TX half duplex mode. This bit is cleared any time 2003/04/04 17 Rev.1.97 RTL8208 Auto-negotiation is restarted or the RTL8208 is reset. 10Base-T-FD - This bit indicates that the Link Partner can support 10Base-T full duplex mode. This bit is cleared any time Auto-negotiation is restarted or the RTL8208 is reset. 10Base-T - This bit indicates that the Link Partner can support 10Base-T half duplex mode. This bit is cleared any time Auto-negotiation is restarted or the RTL8208 is reset. Selector Field - Bits 4:0 reflect the value of the Link Partner's selector field. These bits are cleared any time Auto-negotiation is restarted or the chip is reset, and generally reflect the value of 0001, indicating that the Link Partner is an 802.3 device. 6.7 Register6: Auto-Negotiation Expansion Reg. bit 6.[15:5] 6.4 6.3 6.2 6.1 6.0 Name Reserved Parallel Detection Fault Link Partner Next Page Able Local Next Page Able Page Received Link Partner AutoNegotiation Able Description 1=A fault has been detected via the Parallel Detection function. 0=No fault has been detected via the Parallel Detection function. 1= Link Partner is Next Page able. 0= Link Partner is not Next Page able. 1= RTL8208 is Next Page able. 0= RTL8208 is not Next Page able. (permanently=0) 1= A New Page has been received. 0= A New Page has not been received. If Auto- Negotiation is enabled, this bit means: 1= Link Partner is Auto-Negotiation able. 0= Link Partner is not Auto-Negotiation able. In 100FX or Nway disabled, this bit always =1. Mode RO RO RO RO RO/LH RO Default 0 0 0 0 0 0 (AutoNegotiation) or 1 (100FX) Reserved - Ignore the output of the RTL8208 when these bits are read. Parallel Detection Fault - Bit 4 is a read-only bit that gets latched high when a parallel detection fault occurs in the Auto-negotiation state machine. For further details, please consult the IEEE standard. The bit is reset to `0' after the register is read, or when the chip is reset. Link Partner Next Page Able - Bit 3 returns a `1' when the Link Partner has Next Page capabilities. It has the same value as bit 15 of the Link Partner Ability Register. Local Next Page Able - The RTL8208 does not have Next Page capabilities, so it will always return a `0' when bit 2 is read. Page Received - Bit 1 is latched high when a new link code word is received from the Link Partner, checked and acknowledged. This bit is cleared when the link is lost or the chip is reset. Link Partner Auto-Negotiation Able - Bit 0 returns a `1' when the Link Partner is known to have Auto-negotiation capabilities. Before any Auto-negotiation information is exchanged, or if the Link Partner does not comply with IEEE Auto-negotiation, the bit returns a value of `0'. 2003/04/04 18 Rev.1.97 RTL8208 7. Functional Description 7.1 General 7.1.1 SMI (Serial Management Interface) SMI (Serial Management Interface) is also known as MII Management Interface, which consists of two signals, MDIO and MDC; allowing the MAC controller to control and monitor the state of the PHY. MDC is a clock input for PHY to latch MDIO on its rising edge. The clock can run from DC to 25MHz. MDIO is a bi-directional connection used to write data to, or read data from PHY. The PHY address base is set by pins PHY_ADDR[4:3] and eight ports addresses of RTL8208 are internally 000,001,010,011,100,101,110,and 111. SMI Read/Write Cycles Preamble (32 bits) Read 1........1 Write 1........1 Start (2 bits) 01 01 OP Code (2 bits) 10 01 PHYAD (5 bits) AAAAA AAAAA REGAD (5 bits) RRRRR RRRRR TurnAround (2 bits) Z0 10 Data (16 bits) D.......D D.......D Idle Z* Z* *Z: high-impedance. During idle time, MDIO state is determined by an external 1.5K pull-up resistor. The RTL8208 supports Preamble Suppression, which allows the MAC to issue Read/Write Cycles without preamble bits (but needs at least one Idle for every cycle). However, for the first MII management cycle after power-on reset, a 32-bit preamble is needed. To guarantee the first successful SMI transaction after power-on reset, the MAC should be delayed at least 700us to issue the first SMI Read/Write Cycle relative to the rising edge of reset. 7.1.2 Port Pair Loop Back Mode (PP-LPBK) PP-LPBK mode is enabled by pulling pin 81 high on reset. When in PP-LPBK mode, the ports of the RTL8208 is configured as four pairs, port0 & port1, port2 & port3, port4 & port5, and port 6 & port7. Each pair are set as RMII interface loop back, acting like a signal regeneration /transformation repeater, so a switch controller is not necessary. In PP-LPBK mode, TP port and FX port selection is different from that in normal mode. The TP and FX port selection configuration is as follows: For this table, "U" means UTP port, "F" means Fiber port. PP-LPBK SEL_TXFX[1:0] mode (Pin 99,107) Port0, Port1 (Pin 81) 0 00 U U (normal mode) 01 U U 10 U U 11 F F 1 00 U U (PP-LPBK) 01 U U 10 U F 11 F F Port2, Port3 U U U F U U U F U U U F U U F F Port4, Port5 U U U F U U U F U U U F U F F F Port6, Port7 U U F F U U U F U F F F U F F F Since this configuration is a loop back mode, it uses Full duplex only, and Half duplex is not supported. The loop-back-pair ports should be configured as the same Speed. Although this mode does not effect normal N-Way mode, in order to keep in the same speed for each pair's two ports, there is an auto-detection scheme. This scheme specifies that if one port of the pair is already linked, when the other port is linked later, the earlier link-on port will re-start Auto-negotiation, trying to keep the two ports linked at the same speed. When PP-LPBK mode is set, there are three requirements: It must be based upon RMII mode; no switch controller is connected; and TX_EN[7:0] is pulled down. 2003/04/04 19 Rev.1.97 RTL8208 7.1.3 PHY Address Each transceiver in the RTL8208 will have a unique PHY address for MII management. The address will be set through the PHY address pins. The pins are latched at the trailing end of a reset. Transceiver 1 will have the address AA000, where AA=PHYAD [4:3]. Each internal PHY address is AA000, AA001, AA010, AA011, AA100, AA101, AA110, AA111. Every time an SMI write or read operation is executed, the transceiver compares the PHY address with its own PHY address definition, and the operation is executed only when the addresses match. 7.1.4 Auto-Negotiation For 100/10 TP port, the RTL8208 default setup is Auto-Negotiation enabled. Setting Register 0.12=0 by an SMI write can disable Auto-Negotiation. For a 100FX port, Auto-Negotiation is always disabled. For an Auto-Negotiation enabled port, the RTL8208 will negotiate with its link partner to determine the speed and duplex status. The RTL8208's ability is advertised in Register 4, and , after Auto-Negotiation is finished, the link partner's ability will be stored in Register 5. If the link partner is Auto-Negotiation disabled, the RTL8208 enters a parallel-detection state to identify the speed of the link partner. The RTL8208 will link in the same speed as link partner, but in half duplex mode. Auto-Negotiation is also used to determine Full-duplex flow control. flow control ability is advertised in Register 4.10. The link partner's flow control ability is stored in Register 5.10. See the following section for more information. 7.1.5 Full-Duplex Flow Control If hardware pin TP_pause or 100FX_pause are enabled at power-on reset, Register 5.10=1 and Register 4.10=1. Therefore, after reset is completed: When Auto-Negotiation is enabled, Register 4.10 may be overwritten by the MAC, and Register 5.10 may be updated after N-Way has completed and, Register 5.10 is set as read only for the MAC. When Auto-Negotiation is disabled, Register 5.10 is set to R/W for the MAC through the SMI interface. If the SMI does not write to Register 5.10, it is still Register 5.10=1, which means hardware forced flow control is enabled. 7.2 Initialization and Setup 7.2.1 Reset The RTL8208 is initialized while in a reset state. During reset, each transceiver will be reset simultaneously. There are 3 ways to reset the RTL8208: Power-on auto reset; hardware pin reset; and software reset. The internal power-on auto reset circuit can reset the chip while the reset pin (pin47) is floating. The hardware reset signal must be asserted to pin 47, RESET#, low for at least 100ms. A software reset is implemented by writing Register 0.15=1, which is self clearing. 7.2.2 Setup and configuration The operational modes of the RTL8208 can be configured either by hardware pin (pulled high or low) upon reset or by software programming via accessing the RTL8208 registers through the SMI. Refer to the pin and register description sections. 7.3 10Base-T 7.3.1 Transmit Function When TX_EN is active, TXD from RMII/SMII/SS-SMII is serialized, Manchester-encoded, and driven into the network medium as a packet stream. An on-chip filtering and wave shaping circuit eliminates the need for external filtering. The transmit function is disabled when the link has failed or when Auto-negotiation proceeds. 2003/04/04 20 Rev.1.97 RTL8208 7.3.2 Receive Function The Manchester decoder converts the incoming serial stream when the circuit detects the signal , and the digital serial stream is then converted to 2-bit (RMII) or 1-bit (SMII/SS-SMII) data format. The preamble of the incoming stream is stripped off and regenerated. SFD is generated into RXD once the incoming SFD is detected and data bits entering the elastic buffer are over threshold. 7.3.3 Link Monitor The 10Base-T link pulse detection circuit constantly monitors the RXIP/RXIN pins for the presence of valid link pulses. Auto-polarity is implemented for correcting the detected reverse polarity of the RXIP/RXIN signal pairs. 7.3.4 Jabber Jabber occurs when TX_EN is asserted over 21ms. Both transmit and loopback functions are disabled once jabber occurs. The MII Register 1.1 (Jabber detect) bit is set high until jabber disappears and the bit is read again. The Jabber function is supported in 10-Base-T only, and is not implemented in 100Base-TX. The collision LED of the corresponding port will blink while Jabber occurs. Jabber is dismissed after TX_EN remains low for at least 500ms. 7.3.5 Loopback Loopback mode can be achieved by writing to Register 0.14=1. Loopback mode routes transmitted data at the output of NRZ to the NRZI conversion module, back to the receiving path. This mode is used to check all the device's connection at the 5-bit symbol bus, and verify the operation of the phase locked loop. 7.4 100Base-TX An internal 125MHz clock is generated by an on-chip PLL circuit to synchronize the transmit data or generate the clock signal for the incoming data stream. 7.4.1 Transmit Function Upon detection of TX_EN high, the RTL8208 converts RMII/SMII/SS-SMII TXD to 5 bit code-group and substitutes J/K code-groups for the first 2 code-groups, which are called Start of Stream Delimiter (SSD). 4B5B coding continues for all of the data as long as TX_EN is asserted high. At the end of TX_EN, T/R code-groups are appended to the last data field, which will be stripped off at the remote receiving side. During the inter-packet gap, where TX_EN deasserted, IDLE code-groups are transmitted for the sake of clocking of the remote receiver. The 5-bit serial data stream after 4B5B coding is then scrambled as defined by the TP-PMD Stream Cipher function to flatten the power spectrum energy such that EMI effects can be significantly reduced. This multi-level signaling technology moves the power spectrum energy from high frequency to low frequency, which also benefits EMI emission. Scrambling is not implemented in 100Base-FX. 7.4.2 Receive Function The receive path includes a receiver composed of an adaptive equalizer and DC restoration circuits. These circuits compensate for incoming distortion of the MLT-3 signal. An MLT-3 to NRZI, and NRZI to NRZ converter is used to convert analog signals to digital bit-streams. A PLL circuit is also included to clock data bits exactly with minimum bit error rate. De-scrambler, 5B/4B decoder and serial-to-parallel conversion circuits follow. CRS_DV is asserted no later than when the SSD (Start-of-Stream-Delimiter) is detected within a few bits time (delay due to the elastic buffer as mentioned in the RMII section), and ends toggling once the data in the elastic buffer has been dumped to RXD. 2003/04/04 21 Rev.1.97 RTL8208 Name 0 1 2 3 4 5 6 7 8 9 A B C D E F I J K T R H V V V V V V V V V V 4B Code 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0000* 0101* 0101* 0000* 0000* 1000 0111 0111 0111 0111 0111 0111 0111 0111 0111 0111 5B Code 11110 01001 10100 10101 01010 01011 01110 01111 10010 10011 10110 10111 11010 11011 11100 11101 11111 11000 10001 01101 00111 00100 00000 00001 00010 00011 00101 00110 01000 01100 10000 11001 Definition Data 0 Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 Data 8 Data 9 Data A Data B Data C Data D Data E Data F Idle Start of stream Delimiter, Part 1 Start of stream Delimiter, Part 2 End of stream Delimiter, Part 1 End of stream Delimiter, Part 2 Transmit Error (used to force signaling errors) Invalid code Invalid code Invalid code Invalid code Invalid code Invalid code Invalid code Invalid code Invalid code Invalid code *Treated as an invalid code (mapped to 0111) when received in data field. 4B5B Encoding 7.4.3 Link Monitor In 100Base-TX mode, receive signal energy is detected by monitoring the receive pair for transitions in the signal level. Signal levels are qualified using squelch detect circuits. When no signal or valid signals are detected on the receive pair, the link monitor will enter and remain in the "Link Fail" state where only idle codes will be transmitted. When a valid signal is detected on the receive pair for a minimum period of time, the link monitor will enter the "Link Pass" state and the transmit and receive functions will be enabled. 2003/04/04 22 Rev.1.97 RTL8208 7.4.4 Baseline Wander Compensation The RTL8208 is ANSI TP-PMD compliant and supports input and Base Line Wander (BLW) compensation in 100Base-TX mode. The RTL8208 does not require external attenuation circuitry at its receive inputs, RXIP/RXIN. It accepts TP-PMD compliant waveforms directly, requiring only a 100 termination and a 1:1 transformer. BLW is the change in the average DC content, over time, of an AC coupled digital transmission over a given transmission medium. BLW is a result from the interaction between the low frequency components of a transmitted bit stream and the frequency response of the AC coupling component(s) within the transmission system. If the low frequency content of the digital bit stream goes below the low frequency pole of the AC coupling transformers, then the droop characteristics of the transformers will dominate resulting in potentially serious BLW. If BLW is not compensated for, packet loss will occur. 7.5 100Base-FX The RTL8208 can be configured into 100Base-FX mode through SEL_TXFX[1:0] (RPT_MODE should be 0). According to the setting of SEL_TXFX[1:0], port 7 or port 6/7 or all eight ports can be configured to 100Base-FX operation. RPT_MODE=0 SEL_TXFX[1:0] 2'b00 2'b01 2'b10 2'b11 Port 0 UTP UTP UTP FX Port 1 UTP UTP UTP FX Medium type Port2 Port3 Port4 Port5 Port6 Port7 UTP UTP UTP UTP UTP UTP UTP UTP UTP UTP UTP FX UTP UTP UTP UTP FX FX FX FX FX FX FX FX UTP: 10Base-T/100Base-TX, FX: 100Base-FX. Compared to common 100Base-FX applications, the RTL8208 lacks a pair of differential SD (signal detect) signals to achieve its link monitoring function (patent), which significantly reduces the pin count in this octal PHY. Any of the RTL8208 transceivers may interface with an external 100Base-FX fiber optic device and receiver instead of the magnetics module used with twisted pair cable. The differential transmit and receive data pairs will operate at PECL voltage levels instead of those required for twisted-pair transmission. The data will be encoded using two-level NRZI instead of three-level MLT3. The data stream is not scrambled for fiber-optic transmission. 7.5.1 Transmit Function In 100Base-FX transmission, TXD is processed as 100Base-TX, except without scrambling, before the NRZI stage. Instead of converting to MLT-3 signals, as in 100Base-TX, the serial data stream is driven out as NRZI PECL signals, which enter the fiber transceiver in differential-pairs form. The fiber transceiver should be available working in a 3.3V environment. Refer to the fiber application section for more information. PECL DC characteristics Parameter PECL Input High Voltage PECL Input Low Voltage PECL Output High Voltage PECL Output Low Voltage Symbol Vih Vil Voh Vol Min Vdd-1.16 Vdd-1.81 Vdd-1.02 Max Vdd-0.88 Vdd-1.47 Vdd-1.62 Unit V V V V 7.5.2 Receive Function Signals are received through PECL receiver inputs from the fiber transceiver, and directly passed to the clock recovery circuit for data/clock recovery. The scrambler/descrambler is bypassed in 100Base-FX mode. 2003/04/04 23 Rev.1.97 RTL8208 7.5.3 Link Monitor In 100Base-FX mode, if the RTL8208 receive path detects a valid link word, it enters the link state. If no valid link word is detected, it is in a link down state. Therefore, SD+/- is not necessary. The RTL8208 uses a reduced 100Base-FX interface. 7.5.4 Far-End-Fault-Indication (FEFI) The MII Register 1.4 (Remote Fault indication detected) is a FEFI bit when 100FX is enabled, which indicates FEFI has been detected. FEFI is an alternative in-band signaling method which is composed of 84 consecutive `1' followed by one `0'. From the point of view of the RTL8208, once this pattern is detected 3 times, Register 1.4 is set, which means the transmit path (Remote side's receive path) has some problems. On the other hand, if the RTL8208 detects no valid link pulse on RxOP/N pair, it sends out a FEFI stream pattern, which in turn will cause the remote side to detect a Far-End-Fault indication. This means the RTL8208 sees problems on the receive path. The FEFI mechanism is used only in 100Base-FX applications. 7.5.5 Reduced Fiber Interface The.RTL8208 ignores the underlying SD signal of the fiber transceiver to complete link detection and connection. This is achieved by monitoring RD signals from the fiber transceiver and checking if any link integrity events are met. This significantly reduces pin-count, especially for high-port PHY devices. This is a Realtek patent-pending technology and available only with Realtek product solutions. 7.6 RMII/SMII/SS-SMII The interface to the MAC can be RMII, SMII, or SS-SMII through MODE[1:0]. When floating MODE[1:0] upon power-on reset, the RTL8208 operates in RMII mode (default). MODE[1:0] 2'b1x 2'b00 2'b01 Operation Mode RMII SMII SS-SMII REFCLK Clock input 50MHz, 100ppm 125MHz, 100ppm 125MHz, 100ppm Below illustrates the signals required for each interface: RMII REFCLK SMII REFCLK SYNC SS-SMII REFCLK TX_SYNC RX_SYNC RX_CLK RXD0[7:0] RXD0[7:0] CRS_DV[3:0] CRS_DV[4] CRS_DV[7:5] RXD0[7:0] RXD1[7:0] TX_EN[3:0] TX_EN[4] TX_EN[7:5] TXD0[7:0] TXD1[7:0] TX_CLK TXD0[7:0] TXD0[7:0] 2003/04/04 24 Rev.1.97 RTL8208 7.6.1 RMII (Reduced MII) The RTL8208 meets all of the RMII requirements outlined in the RMII Consortium specifications. The main advantage introduced by RMII is pin count reduction; e.g., it operates with only one 50Mhz reference clock for both the TX and RX sides without separate clocks needed for both paths, as with the MII interface. However, some hardware modification is needed for this change, the most important and outstanding of which is the presence of an elastic buffer for absorption of the frequency difference between the 50MHz reference clock and the clocking information of the incoming data stream. Another change implemented is that the MII RXDV and Carrier_Sense are merged into one signal, CRS_DV, which is asserted high while detecting incoming packet data. When internal Carrier_Sense de-asserted, CRS_DV is de-asserted when the first di-bit of a nibble is presented onto RXD[1:0] synchronously to REFCLK. If there is still data in the FIFO that has not yet been presented onto RXD[1:0], then on the second di-bit of a nibble CRS_DV reasserts. This pattern of assertion and de-assertion continues until all received data in the FIFO has been presented onto RXD[1:0] CRS_DV[7:0] RXD0[7:0] RXD1[7:0] CRS_DV[7:0] RXD0[7:0] RTL8208 X1 TX_EN[7:0] TXD0[7:0] TXD1[7:0] REFCLK 8-port MAC RXD1[7:0] RTL8208 X1 TX_EN[7:0] TXD0[7:0] TXD1[7:0] REFCLK 8-port MAC X2 25MHz 50MHz oscillator RMII Signal Diagram 50MHz Oscillator Solution RMII Signal Diagram 25MHz Crystal Solution 7.6.2 SMII (Serial MII) The RTL8208 also supports SMII interface to MAC, which allows a further reduction in the number of signals. As illustrated below, both the MAC and RTL8208 are synchronous to a 125MHz reference clock. SYNC TXD0[7:0] 8-port MAC X1 RTL8208 RXD0[7:0] REFCLK 125MHz oscillator SMII Signal Diagram 2003/04/04 25 Rev.1.97 RTL8208 Receive Path Receive data and control information are signaled in 10-bit segments. SYNC signal is used to delimit the 10-bit segments. MAC is responsible to generate these SYNC pulses every ten clocks. For 100Mbps mode, each segment represents a byte of data. However, for 10Mbps mode, each segment is repeated ten times to represent a byte of data. The receive sequence contains all of the information defined on the standard MII receive path. CRS X RX_DV 0 RXD0 RXER from previous frame RXD1 Speed 0 =10Mbps 1 =100Mbps RXD2 Duplex 0 = Half 1 = Full RXD3 Link 0 = Down 1 = Up RXD4 RXD5 RXD6 RXD7 1 Jabber Upper Nibble False Carrier 0 = OK 0 = OK 0 = Invalid 1 = Detected 1 = Detected 1 = Valid X 1 One Data Byte (Two MII Data Nibbles) SMII Reception Encoding 1 REFCLK 2 3 4 5 6 7 8 9 10 SYNC RXD[0] CRS RXDV RXD0 RXD1 RXD2 RXD3 RXD4 RXD5 RXD6 RXD7 SMII Reception Transmit Path Transmit data and control information are signaled in 10-bit segments. SYNC signal is used to delimit the 10-bit segments. MAC is responsible to generate these SYNC pulses every ten clocks. For 100Mbps mode, each segment represents a byte of data. However, for 10Mbps mode, each segment is repeated ten times to represent a byte of data. TXER X TXEN 0 TXD0 X TXD1 X TXD2 X TXD3 X TXD4 X TXD5 X TXD6 X TXD7 X X 1 One Data Byte (Two MII Data Nibbles) SMII Transmission Encoding 1 REFCLK 2 3 4 5 6 7 8 9 10 SYNC TX_ER TX_EN TXD0 TXD1 TXD2 TXD3 TXD4 TXD5 TXD6 TXD7 SMII Transmission Collision Detection The RTL8208 does not indicate that a collision has occurred. It is left up to the MAC to detect the assertion of both CRS_DV and TX_EN. 2003/04/04 26 Rev.1.97 RTL8208 7.5.3 SS-SMII (Source Synchronous -Serial MII) Source-Synchronous SMII is designed for applications requiring a trace delay of more than 1ns. Three signals are added to the SMII interface: RX_SYNC, RX_CLK, TX_CLK; and the SYNC of SMII is modified to TX_SYNC in SS-SMII. TX_SYNC TXD0[7:0] TX_CLK 8-port MAC X1 RX_SYNC RXD0[7:0] RX_CLK REFCLK RTL8208 125MHz oscillator SS-SMII Signal Diagram Receive Path Receive data and control information are signaled in 10-bit segments. RX_SYNC signal is used to delimit the 10-bit segments. RTL8208 is responsible to generate these RX_SYNC pulses every ten clocks. For 100Mbps mode, each segment represents a byte of data. However, for 10Mbps mode, each segment is repeated ten times to represent a byte of data. The receive sequence contains all of the information defined on the standard MII receive path. 1 RX_CLK 2 3 4 5 6 7 8 9 10 RX_SYNC RXD[0] CRS RXDV RXD0 RXD1 RXD2 RXD3 RXD4 RXD5 RXD6 RXD7 SS-SMII Reception Transmit Path Transmit data and control information are signaled in 10-bit segments. TX_SYNC signal is used to delimit the 10-bit segments. MAC is responsible to generate these TX_SYNC pulses every ten clocks. For 100Mbps mode, each segment represents a byte of data. However, for 10Mbps mode, each segment is repeated ten times to represent a byte of data. The receive sequence contains all of the information defined on the standard MII receive path. The PHY can sample one of the ten segments. 1 TX_CLK 2 3 4 5 6 7 8 9 10 TX_SYNC TXD[0] TX_ER TX_EN TXD0 TXD1 TXD2 TXD3 TXD4 TXD5 TXD6 TXD7 SS-SMII Transmission Collision Detection The RTL8208 does not indicate that a collision has occurred. It is left up to the MAC to detect the assertion of both CRS_DV and TX_EN. 2003/04/04 27 Rev.1.97 RTL8208 7.7 Power Saving and Power Down Mode 7.7.1 Power Saving Mode The RTL8208 implements a power saving mode on a per port basis. One port automatically enters power saving mode 10 seconds after the cable is disconnected from it, regardless of whether the RTL8208's operation mode is Nway or Force mode. Once one port enters power saving mode, it transmits normal link pulses only on its TXOP/TXON pins and keeps monitoring RXIP/RXIN to try to detect any incoming signals , which might be 100Base-TX MLT-3 idle pattern, 10Base-T link pulses or Nway's FLP (fast link pulses). After it detects any incoming signals, it wakes up from the power saving mode and operates in the normal mode according to the result of the connection. Power saving mode is not supported when in 100FX operation. 7.7.2 Power Down Mode Setting Register 0.11through the SMI interface forces the corresponding port of the RTL8208 to enter power down mode, which disables all transmit/receive functions and RMII functions on that port, except SMI (MDC/MDIO management interface). 7.8 LED Configuration The RTL8208 supports serial LED status streams for LED display. The forms of LED status streams, as shown below, are controlled by LEDMODE[1:0] pins, which are latched upon reset. All LED statuses are represented as active-low, except Link/Act in Bi-color LED mode, whose polarity depends on Spd status. LEDMODE[1:0] Mode Output sequences 00 3-bit serial stream Col/Fulldup, Link/Act, Spd 01 2-bit serial stream Spd, Link/Act 10 3-bit for Bi-color LED Col/Fulldup, Link/Act, Spd LED Statuses Col/Fulldup Link/Act Description Col, Full duplex Indicator. Blinking every 43ms when collision happens. Low for full duplex, and high for half duplex mode. Link, Activity Indicator. For 3-bit serial stream mode, low for link established. For 3-bit Bi-color LED mode, Link/Act is high for link established when speed is low (100Mb/s); Link/Act is low for link established when speed is high (10Mb/s). Link/Act Blinks every 43ms when the corresponding port is transmitting or receiving. Speed Indicator. Low for 100Mb/s, and high for 10Mb/s. Spd 7.8.1 LED Blinking Time LED blinking time can be set to 120ms by setting LED_BLNK_TIME=0. The LED statuses supporting 43/120ms blinking time are Col/Fulldup, Link/Act. For status Link/Act/Spd, the LED blinking time is not affected by LED_BLNK_TIME. 2003/04/04 28 Rev.1.97 RTL8208 7.8.2 Serial Stream Order Every bit stream is output port by port, from port0 to port7 with Col/Fulldup as the first bit in a port stream. For 2-bit serial stream mode, the sequence is Spd, then Link/Act. The following diagrams illustrate the sequences in 3-bit and 2-bit serial stream mode. 2.56 us 2.56 us 2.56 us 2.56 us 2.56 us 2.56 us 2.56 us 2.56 us 2.56 us LEDCLK 1 Col/Dup 2 Link/Act Spd 3 19 Col/Dup 20 Link/Act 21 Spd 22 Col/Dup 23 Link/Act 24 Spd LEDDTA Port 0 3-bit serial stream Port 6 3-bit serial stream Port 7 3-bit serial stream 3-Bit Serial Stream Mode 2.56 us 2.56 us 2.56 us 2.56 us 2.56 us 2.56 us 2.56 us LEDCLK 1 Spd 2 Link/Act 13 Spd 14 Link/Act 15 Spd 16 Link/Act LEDDTA Port 0 2-bit serial stream Port 6 2-bit serial stream Port 7 2-bit serial stream 2-Bit Serial Stream Mode VDD LEDDTA LEDCLK QA QB QC CLK 74164 QD VDD QE QF B QG QH CLR A port 7 Spd LED port 7 Link/Act LED port 7 Col/Dup LED port 6 Spd LED port 6 Link/Act LED port 6 Col/Dup LED port 5 Spd LED port 5 Link/Act LED QA QB QC CLK 74164 QD VDD QE QF B QG QH CLR A port 5 Col/Dup LED port 4 Spd LED port 4 Link/Act LED port 4 Col/Dup LED port 3 Spd LED port 3 Link/Act LED port 3 Col/Dup LED port 2 Spd LED QA QB QC CLK 74164 QD VDD QE QF B QG QH CLR A port 2 Link/Act LED port 2 Col/Dup LED port 1 Spd LED port 1 Link/Act LED port 1 Col/Dup LED port 0 Spd LED port 0 Link/Act LED port 0 Col/Dup LED External circuit for 3-bit serial LED mode 2003/04/04 29 Rev.1.97 RTL8208 VDD port 7 Link/Act LED port 7 Spd LED port 6 Link/Act LED port 6 Spd LED port 5 Link/Act LED port 5 Spd LED port 4 Link/Act LED port 4 Spd LED LEDDTA LEDCLK QA QB QC CLK 74164 QD VDD QE QF B QG QH CLR A QA QB QC CLK 74164 QD VDD QE QF B QG QH CLR A port 3 Link/Act LED port 3 Spd LED port 2 Link/Act LED port 2 Spd LED port 1 Link/Act LED port 1 Spd LED port 0 Link/Act LED port 0 Spd LED External circuit for 2-bit serial LED mode 7.8.3 Bi-Color LED For 3-bit Bi-color LED mode, Link/Act and Spd are used for one Bi-color LED package, which is a single LED package with two LEDs connected in parallel with opposite polarities. Yellow Spd 0 0 1 Link/Act Indication Bi-Color state 0 No Link Off 1 100Mb/s Link up Green 0 10Mb/s Link up Yellow Spd Link/Act Green 7.9 Crossover Detection and Auto Correction During the link setup phase, the RTL8208 checks for reception of active signals on every port to determine if a connection can be established. If the receive data pin pair is connected to receive pin pair of the peer device (and vice versa), the RTL8208 will automatically change its configuration to swap receive data pins with transmit data pins. In other words, the RTL8208 can adapt automatically to a peer device's configuration. If a port is connected to a PC or NIC with an MDI-X interface with a crossover cable, the RTL8208 will reconfigure the port to provide an MDI-X interface to ensure a proper connection. This will effectively replace the eight-DIP switch commonly used for reconfiguring a port on a hub or switch. By pulling-up EN_AUTOXOVER, the RTL8208 can identify the type of connected cable to adjust its port as for MDI or MDIX operation. When switching to MDI mode, the RTL8208 uses TXOP/N as transmit pairs, and when switching to MDIX mode, the RTL8208 uses RXIP/N as transmit pairs. The same is true for the receive pairs. This function is port-based implemented. Pulling-down EN_AUTOXOVER will disable this function and the RTL8208 operates in MDI mode, in which TXOP/N represents transmit pairs and RXIP/N represents receive pairs. 2003/04/04 30 Rev.1.97 RTL8208 7.10 Polarity Detection and Auto Correction For better noise immunity and lower interference to ambient devices, the Ethernet electrical signal on a twisted pair cable is transmitted in differential forms. That is, the signal is transmitted on two wires for each direction with inverse polarities (+/-). If wiring on the connector is faulty or a faulty transformer is used, the two inputs to a transceiver may carry signals with opposite but incorrect polarities. As a direct consequence, the transceiver will not work properly. When the RTL8208 operates in 10Base-T mode, it automatically reverses the polarity of its two receiver input pins if it detects that the polarities of the incoming signals on the pins are incorrect. However, this feature is unnecessary when the RTL8208 is operating in 100Base-TX mode. 7.11 2.5V Power Generation The RTL8208 uses a PNP transistor to generate 2.5V from the 3.3V power supply. This 2.5V provides for digital core and analog receive circuits. Once your system needs more than one RTL8208 chip (greater than 8 ports), do not use one PNP transistor for all of the RTL8208 chips even if the rating is enough. Instead, use one transistor for each RTL8208. Do not connect any beads directly between the collector of PNP transistor and VDDAL. This will affect the stability of the 2.5V power significantly if the bead exists. 3.3V 3.3V RTL8208 VDDAH VDDAH: 3.3V VDDAL: 2.5V 2SB1197K Ic(max.)=800mA VCTRL VDDAL 2.5V 47uF 0.1uF Using a PNP Transistor to Produce 2.5V The power transistor is a 2SB1197K, and follows the following specifications. Absolute maximum ratings (Ta=25C) Parameter Symbol Collector-base voltage VCBO Collector-emitter voltage VCEO Emitter-base voltage VEBO Collector current IC Collector power dissipation PC Junction temperature Tj Storage temperature Tstg For more information, refer to http://www.rohm.com Limits -40 -32 -5 -0.8 0.2 150 -55~+150 Unit V V V A(DC) W C C 2003/04/04 31 Rev.1.97 RTL8208 8. Design and Layout Guide In order to achieve maximum performance for the RTL8208, good design attention is required throughout the design and layout process. The following recommendations can help to implement a high performance system. 8.1 General Guidelines * Create a good power source, minimizing noise from switching power supply circuits. * Verify the quality of the components, such as clock source and transformer, to meet the application requirements. * Keep power and ground noise levels below 150mV. * Use bulk capacitors (4.7uF-10uF) between the power and ground planes. * Use 0.1uF decoupling capacitors to reduce high-frequency noise on the power and ground planes. * Keep decoupling capacitors as close as possible to the RTL8208 power pins. * Provide termination for all TXOP/N and RXIP/N. 8.2 Differential Signal Layout Guidelines * Keep differential pairs as close as possible and route both traces as identically as possible. * Avoid vias and layer changes if possible. * Keep the different pairs away from each other. 8.3 Clock Circuit * The clock should be 25M/50MHz/125MHz 100ppm with jitter less than 0.5ns. * If use 50MHz or 125MHz as clock source, make the length of clock path to RTL8208 equal to the length to MAC as possible. The length difference should under 1 inch. * If use 50MHz, please put a damping resistor at clock source side. * If possible, make clock trace smooth, strait, and surrounded by ground traces to minimize high-frequency emissions. 8.4 2.5V power * Do not connect a bead directly between the collector of the PNP transistor and VDDAL. This will affects the stability of the 2.5V power significantly if a bead exists. * Use a bulk of capacitor (4.7uF-10uF) between the collector of PNP transistor and ground plane. * Do not use one PNP transistor for more than one RTL8208 chip, even if the rating is enough. Use one transistor for each RTL8208. 8.5 Power Planes * If the layout board size is small, it is better not to divide the power plane into digital and analog power planes. * Use 0.1uF decoupling capacitors and bulk capacitors between power plane and ground plane. 8.6 Ground Planes * If the layout board size is small, keep the system ground region as one continuous, unbroken plane. * Place a moat (gap) between the system ground and chassis ground. * For better ESD test performance, please use iron case, and put screw to connect frame ground to iron case. 8.7 Transformer Options * The magnetics support 1:1 turn ratio on both the transmit and receive paths are valid for RTL8208. There are many vendors improving their magnetics design to meet this requirement, and several are listed below. Vendor Pulse Magnetic 1 Model H1164 ML164 Vendor BothHand GTS Model 40ST1041AX FC-638L * The center-tap of the primary side of the transformer should not be connected to ground with capacitors, because of the RTL8208's special design. 2003/04/04 32 Rev.1.97 RTL8208 9. Application information 9.1 10Base-T/100Base-TX Application RXIP RXIN 50 1% 50 1% 0.1uF Pulse H1164 1:1 RJ45 1 2 3 4 RTL8208 TXOP 50 1% 50 1% 0.1uF 5 1:1 6 7 8 TXON IBREF 1.96, 1% 75 3 0.1uF/3KV Chasis GND 10Base-T/100Base-TX Diagram The Central Tap in the primary side of H1164 must be left floating, and cannot be bypassed to GND via capacitor. 2003/04/04 33 Rev.1.97 RTL8208 9.2 100Base-FX Application (3.3V fiber transceiver) VCC_RX (3.3V) 82 DELTA OPT-155A2H1 RXIP RXIN 82 130 130 1 GND_RX 2 RD+ 3 RD- RTL8208 VCC_TX (3.3V) VCC_RX (3.3V) VCC_TX (3.3V) 4 SD 5 VCC_RX 6 VCC_TX 7 TD- 82 TXON TXOP 82 130 130 8 TD+ 9 GND_TX Chasis GND 1.96, 1% 100Base-FX Application (3.3V Fiber Transceiver) 2003/04/04 34 Rev.1.97 RTL8208 10. Electrical Characteristics 10.1 Absolute Maximum Ratings WARNING: Absolute maximum ratings are limits beyond which may cause permanent damage to the device or affect device reliability. All voltages are specified reference to GND unless otherwise specified. Parameter Minimum Maximum Units Storage Temperature -55 +150 C Vcc Supply Referenced to GND -0.5 +4.0 V Digital Input Voltage -0.5 VDD V DC Output Voltage -0.5 VDD V 10.2 Operating Range Parameter Ambient Operating Temperature(Ta) 3.3V Supply Voltage Range(VDDAH) 2.5V Supply Voltage Range(VDDAL,VDD) Minimum 0 3.15 2.375 Maximum +50 3.45 2.625 Units C V V 10.3 DC Characteristics Parameter Power Supply Current for 2.5V Symbol Conditions Icc 10 Base-T, idle 10 Base-T, Peak continuous 100% utilization 100 Base-TX, idle 100 Base-TX, Peak continuous 100% utilization Power saving Power down Icc 10 Base-T, idle 10 Base-T, Peak continuous 100% utilization 100 Base-TX, idle 100 Base-TX, Peak continuous 100% utilization Power saving Power down PS 10 Base-T, idle 10 Base-T, Peak continuous 100% utilization 100 Base-TX, idle 100 Base-TX, Peak continuous 100% utilization Power saving Power down Vih Vil Iin Cin Voh Vol Min Typical Max Power Supply Current for 3.3V Total Power Consumption for all 8 ports 81.2 88.9 125.5 145.7 76.7 15.5 88.5 499.2 370.7 371.3 48.1 3.3 495 1870 1537 1590 350 50 1.5 -10 3 2.25 0 2.75 0.25 1.0 10 Units mA mA mW TTL Input High Voltage TTL Input Low Voltage TTL Input Current TTL Input Capacitance Output High Voltage Output Low voltage V V uA pF V V 2003/04/04 35 Rev.1.97 RTL8208 Parameter Output Tristate Leakage Current TX+/- Output Current High TX+/- Output Current Low TX+/- Output Current High TX+/- Output Current Low RX+/- Common-mode input voltage RX+/- Differential input resistance Receiver, 10BaseT Differential Input Resistance Input Squelch Threshold 20 340 k mV SYM |IOZ| Conditions Min Typical Max 10 20 Units uA mA uA mA uA V k Transmitter, 100Base-TX (1:1 Transformer Ratio) IOH IOL Transmitter, 10Base-T(1:1 Transformer Ratio) IOH IOL Receiver, 100Base-TX 0 50 0 1.6 20 10.4 AC Characteristics Parameter Differential Output Voltage, peak-to-peak Differential Output Voltage Symmetry Differential Output Overshoot Rise/Fall time Rise/Fall time imbalance Duty Cycle Distortion Timing jitter Differential Output Voltage, peak-to-peak TP_IDL Silence Duration TD Short Circuit Fault Tolerance TD Differential Output Impedance (return loss) TD Common-Mode Output Voltage Transmitter Output Jitter RD Differential Output Impedance (return loss) Harmonic Content Start-of-idle Pulse width VOD SYM VOD VOS VOO tr ,tf |tr - tf| Deviation from best-fit time-grid, 010101 ... Sequence Idle pattern Transmitter, 10Base-T 50 from each output to Vcc, all pattern Period of time from start of TP_IDL to link pulses or period of time between link pulses Peak output current on TD short circuit for 10 seconds. Return loss from 5MHz to 10MHz for reference resistance of 100 . Terminate each end with 50 resistive load. Return loss from 5MHz to 10MHz for reference resistance of 100. dB below fundamental, 20 cycles of all ones data TP_IDL width 10.5 Conditions Transmitter, 100Base-TX 50 from each output to Vcc, Best-fit over 14 bit times 50 from each output to Vcc, |Vp+|/|Vp-| Percent of Vp+ or Vp10-90% of Vp+ or VpMin Typical Max Units V % % ns ps ps ns V 1.938 99.3 3.29 4.3/3.4 910 175 1.0 4.27 15.75 ms mA 12.4 25.5 dB mV Ecm 14 25 ns dB dB ns 2003/04/04 36 Rev.1.97 RTL8208 10.5 Digital Timing Characteristics Parameter Active TX_EN Sampled to first bit of "J on MDI output Inactive TX_EN Sampled to first bit of "T on MDI output TX Propagation Delay First bit of "J on MDI input to CRS_DV assert First bit of "T on MDI input to CRS_DV de-assert RX Propagation Delay TX Propagation Delay TX_EN to MDI output SYM Conditions 100Base-TX Transmit System Timing Min Typical Max 12 16 12 8 18 17 6 6 Units Bits Bits Bits Bits Bits Bits Bits Bits Bits Bits Bits ms ms ms ms ns ns ns ns ns ns MHz ns ns ns 11 15 tTXpd From TXD[1:0] to TXOP/N 100Base-TX Receive System Timing From RXIP/N to CRS_DV From RXIP/N to CRS_DV tRXpd tTXpd From RXIP/N to RXD[1:0] 10Base-T Transmit System Timing From TXD[1:0] to TXOP/N From TX_EN assert to TXOP/N 10Base-T Receive System Timing Preamble on RXIP/N to CRS_DV asserted TP_IDL to CRS_DV de-asserted 11 6 16 15 5 5 12 8 9 43 43 60 60 2 2 4 2 2 2.5 10 70 Carrier Sense Turn-on delay tCSON tCSOFF Carrier Sense Turn-off Delay tRXpd From RXIP/N to RXD[1:0] RX Propagation Delay LED timing tLEDon While LED blinking LED On Time tLEDoff While LED blinking LED Off Time Jabber timing (10Base-T only) Jabber Active From TX_EN=1 to Jabber asserted Jabber de-assert From TX_EN=0 to Jabber de-asserted RMII Timing TXD, TX_EN Setup time TXD [1:0], TX_EN to REFCLK rising edge setup time TXD, TX_EN Hold time TXD [1:0], TX_EN to REFCLK rising edge hold time RXD, CRSDV, RXER to Output delay from REFCLK rising edge to RXD REFCLK delay [1:0], CRSDV, RXER SMII Timing TXD, SYNC Setup time TXD, SYNC to REFCLK rising edge setup time TXD, SYNC Hold time TXD SYNC to REFCLK rising edge hold time RXD, to REFCLK delay Output delay from REFCLK rising edge to RXD SMI Timing MDC MDC clock rate MDIO Setup Time Write cycle MDIO Hold Time Write cycle MDIO output delay relative Read cycle to rising edge of MDC 9 12 120 120 80 80 3.5 25 10 10 2003/04/04 37 Rev.1.97 RTL8208 10.6 Thermal Data Heat generated by the chip causes the temperature rise of the package. If the temperature of the chip (Tj, junction temperature) is beyond the design, there will be negative effects on operation and the life of IC package. It's necessary to develop a switch with a reasonable environment (Ta, ambient temperature) in a closed case to achieve a stable and reliable system, via supporting sufficient heat dissipation capability either through heat sink or electrical fan. However, to estimate the possible Ta is necessary since as the power density increases, the thermal management is getting more critical. Thermal parameters are defined as below according to JEDEC standard JESD 51-2, 51-6: 1. ja( Thermal resistance from junction to ambient), represents the resistance to the heat flows from the chip to ambient air. It's an index of heat dissipation capability. Lower ja means better thermal performance. ja = (Tj - Ta) / Ph Where Tj is the junction temperature Ta is the ambient temperature Ph is the power dissipation 2. jc (Thermal resistance from junction to case), represents the resistance to the heat flows from the chip to package top case. jc is important when external heat sink is attached on package top. jc = (Tj - Tc) / Ph, where Tj is the junction temperature Ta Tj Tc Cross-section of 128 PQFP Thermal Operating Range Parameter Junction operating temperature Ambient operating temperature Thermal resistances Parameter Thermal resistance: junction to ambient Thermal resistance: junction to case SYM Tj Ta Conditions Min 0 0 Typical Max 25 125 25 65 Units C C SYM ja jc Conditions 2 layer PCB, 0 ft/s airflow 2 layer PCB, 0 ft/s airflow Min Typical Max 30.1 14.4 Units C/W C/W * PCB conditions (JEDEC JESD51-7) : dimensions : 76.2 x 114.3 mm, thickness : 1.6mm 2003/04/04 38 Rev.1.97 RTL8208 11. Mechanical Dimensions Symbol A A1 A2 b c D E e HD HE L L1 Y Dimension in inch Min Typical Max 0.134 0.004 0.010 0.036 0.102 0.112 0.122 0.005 0.009 0.013 0.002 0.006 0.010 0.541 0.551 0.561 0.778 0.787 0.797 0.010 0.020 0.030 0.665 0.677 0.689 0.902 0.913 0.925 0.027 0.035 0.043 0.053 0.063 0.073 0.004 0 12 Dimension in mm Min Typical Max 3.40 0.10 0.25 0.91 2.60 2.85 3.10 0.12 0.22 0.32 0.05 0.15 0.25 13.75 14.00 14.25 19.75 20.00 20.25 0.25 0.75 0.5 16.90 17.20 17.50 22.90 23.20 23.50 0.68 0.88 1.08 1.35 1.60 1.85 0.10 0 12 1. Dimension D & E do not include interlead flash. 2. Dimension b does not include dambar protrusion/intrusion. 3. Controlling dimension : Millimeter 4. General appearance spec. should be based on final visual inspection spec. TITLE : 128 QFP (14x20 mm ) PACKAGE OUTLINE -CU L/F, FOOTPRINT 3.2 mm LEADFRAME MATERIAL : APPROVE DOC. NO. 530-ASS-P004 VERSION 1 PAGE OF CHECK DWG NO. Q128 - 1 DATE Oct. 08 1998 REALTEK SEMI-CONDUCTOR CO., LTD 2003/04/04 39 Rev.1.97 RTL8208 Realtek Semiconductor Corp. Headquarters 1F, No. 2, Industry East Road IX, Science-based Industrial Park, Hsinchu, 300, Taiwan, R.O.C. Tel: 886-3-5780211 Fax: 886-3-5776047 WWW: www.realtek.com.tw 2003/04/04 40 Rev.1.97 |
Price & Availability of RTL8208
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |